1 UT54ACTS04E hex inverters july, 2013 datasheet www.aeroflex.com/logic features ? 0.6 ?? m ? crh cmos process - latchup immune ? high speed ? low power consumption ? wide power supply operating range of 3.0v to 5.5v ? available qml q or v processes ? 14-pin flatpack ? UT54ACTS04E - smd - 5962-96517 description the UT54ACTS04E is a hex invete r. the circuit performs the boolean functions y = a ? b or y = a + b in positive logic. the device is characterized over full military temperature range of -55 ? c to +125 ? c. function table logic symbol pinout 14-lead flatpack top view logic diagram input output a y h l l h note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. y1 y2 y3 y4 (1) a1 (5) a3 (11) a5 (13) a6 1 (3) a2 (9) a4 (2) (10) (12) (4) (8) y5 y6 (6) v dd a6 y6 a5 y5 a4 y4 a1 y1 a2 y2 a3 y3 v ss 114 213 312 411 510 69 78 y4 y3 y1 y2 y6 y5 a4 a3 a1 a2 a6 a5
2 operational environment 1 notes: 1. logic will not latchup during radiation exposu re within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1.stresses outside the listed abso lute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits in dicated in the operational s ections is not reco mmended. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. 2. per mil-std-883, method 1012.1, section 3.4.1, p d = (t j(max) - t c(max) ) / ? jc recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 108 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 ? c t j maximum junction temperature +175 ? c t ls lead temperature (soldering 5 seconds) +300 ? c ? jc thermal resistance junction to case 15.5 ? c/w i i dc input current ? 10 ma p d 2 maximum power dissipation permitted @ tc=125 o c 3.2 w symbol parameter limit units v dd supply voltage 3.0 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 ? c
3 dc electrical characteristics (pre and post-radiation)* (v dd = 3.3v to 5.5v; v ss = 0v 6 , -55 ? c < t c < +125 ? c) ; unless otherwise noted, tc is pe r the temperature range ordered symbol description condition min max unit v il1 low-level input voltage 1 v dd from 4.5v to 5.5v 0.8 v v il2 low-level input voltage 1 v dd from 3.0v to 3.6v 0.8 v v ih1 high-level input voltage 1 v dd from 4.5v to 5.5v 0.5 v dd v v ih2 high-level input voltage 1 v dd from 3.0v to 3.6v 2.0 v i in input leakage current v in = v dd or v ss -1 1 ? a v ol1 low-level output voltage 3 i ol = 8ma v dd = 4.5v to 5.5v 0.4 v v ol2 low-level output voltage 3 i ol = 6ma v dd = 3.0v to 3.6v 0.4 v v oh1 high-level output voltage 3 i oh = -8ma v dd from 4.5v to 5.5v 0.7 v dd v v oh2 high-level output voltage 3 i oh = -6ma v dd from 3.0v to 3.6v 2.4 v i os1 short-circuit output current 2 ,4 v o = v dd and v ss v dd from 4.5v to 5.5v -200 200 ma i os2 short-circuit output current 2 ,4 v o = v dd and v ss v dd from 3.0v to 3.6v -100 100 ma i ol1 low level output current 8 v in = v dd or v ss v ol = 0.4v v dd from 4.5v to 5.5v 8 ma i ol2 low level output current 8 v in = v dd or v ss v ol = 0.4v v dd from 3.0v to 3.6v 6 ma i oh1 high level output current 8 v in = v dd or v ss v oh = v dd -0.4v v dd from 4.5v to 5.5v -8 ma i oh2 high level output current 8 v in = v dd or v ss v oh = v dd -0.4v v dd from 3.0v to 3.6v -6 ma p total1 power dissipation 2, 7 c l = 50pf v dd = 4.5v to 5.5v 1 mw/ mhz
4 notes: * for devices procured with a total ionizing dose tolerance guar antee, the post-irrad iation performance is guaranteed at 25c p er mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. functional tests are conducted in accordance with mil-std-883 with th e following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density ? 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buffer) times fre quency should no t exceed 3,765pf/ mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifica tion and when design changes may affect th e value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50 mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. power dissipation specifi ed per switching output. 8. parameter guaranteed by design an d characterization, but is not tested. ac electrical characteristics (pre and post-radiation)* (v dd = 3.0v to 5.5v; v ss = 0v 1 , -55 ? c < t c < +125 ? c); unless otherwise noted, tc is per the temperature range ordered notes: * for devices procured with a total ionizing dose tolerance guar antee, the post-irrad iation performance is guaranteed at 25c p er mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. maximum allowable relative shift equals 50mv. p total2 power dissipation 2, 7 c l = 50pf v dd = 3.0v to 3.6v 0.5 mw/ mhz i ddq quiescent supply current v in = v dd or v ss v dd from 3.6v to 5.5v 10 ? a ? i ddq quiescent supply current delta for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz v dd = 0v 15 pf c out output capacitance 5 ? = 1mhz v dd = 0v 15 pf symbol parameter condition v dd minimum maximum unit t plh input to yn c l = 50pf 3.0v to 3.6v 2 14 ns 4.5v to 5.5v 1 7 t phl input to yn c l = 50pf 3.0v to 3.6v 2 14 ns 4.5v to 5.5v 1 7
packaging 1. all exposed metallized ar eas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in accordance with mil-prf- 38535. 4. dimension symbol is in accordance with mil- prf-38533. 5. lead position and cola narity are not measured. figure 1. 14-lead flatpack
UT54ACTS04E: smd drawing number: 96517 = UT54ACTS04E device type: 02 = 1 rad(si)/sec package type: x = 14-lead ceramic botto m-brazed dual-in-line flatpack lead finish: (notes 1 & 2) a = solder c = gold x = optional 5962 ***** ** * * * * total dose: (notes 3 & 4) r = 1e5 rads(si) f = 3e5 rads(si) g = 5e5 rads(si) h = 1e6 rads(si) 03 = 50 to 300 rads(si)/sec class designator: q = qml class q v = qml class v notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when or dering, part marking will match th e lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. for protot ype inquiries, contact factory. 4. device type 02 is only offered with a tid tolerance guarantee of 3e5 rads(si) or 1e6 rads(si) and is tested in accordance wi th mil-std-883 test method 1019 condition a and section 3.11.2. device type 03 is only offered with a tid tolera nce guarantee of 1e5 rads(si), 3e5 rads(si) , and 5e5 rads(si), and is tested in accordance with mil-std-88 3 test method 1019 condition a.
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